Test Set Minimization for Sequential VLSI Circuits Under Power or Time Constraints

This paper deals with two problems arising during the testing of sequential VLSI circuits, namely the test sequence compaction problem and the power minimization problem. Here is presented a unified model for both problems and is developed a common algorithmic framework to solve either one of these two problems. In this framework a fast and efficient heuristic subsequence selection method is implemented that constructs a good initial solution with the aid of a gain metric. Then, continuing from this initial solution, an exact Branch and Bound algorithm is employed to search for an optimal solution, specifically tailored for these problems so as to speed up the search process. Experimental results that are presented, comparing the proposed algorithm with other solvers from literature, show the effectiveness of the proposed method. Key-Words: Sequential Digital Circuits, Sequence Compaction, Test Generation, Set Cover methods.